In this tutorial we simulate a nanosheet-based device comprised of a III-V channel material. Nanosheet device types allow simulating the properties of quasi-planar devices where effects due to the semiconductor’s finite width are explicitly treated. To set up this simulation start a new M* workspace and set input parameters as:
- Device select Double-gate nanosheet as the device type and enter geometrical parameters in accordance with figure 1 and as shown below in figure 2. Once you have finished, check the geometry corresponds to the intended design by visualising it in the Preview tab
- Material select In(0.53)Ga(0.47)As, (010)/〈100〉, n-type and cycle through regions to set a target carrier concentration of 5 × 1019 cm-3 in source and drain extensions (i.e. regions 1 & 3), and zero in region 3. Input an oxide relative permittivity of εr = 4.0 (low-κ oxide) in source and drain extensions, and a value εr = 20.0 (high-κ oxide) in the channel. The low-κ oxide will reduce capacitive coupling between the gate electrode and source/drain extension regions
- Control select fast uncoupled-mode space (FUMS) as the mode-space method, and subbands to 6. Set a gate voltage sweep covering the [0.0,0.85] V range in steps of 0.05 V, and a drain voltage of 0.05 V. Enable saving electric potentials and carrier densities and set Save every  bias points to reduce disk space usage. Set the same convergence parameters as in previous tutorials and shown in figure 4
Click Run to begin the simulation. Once completed, you may visualise the 3D quantities to observe the influence of the device’s finite width on both electric potential and carrier density, as shown in figures 5 and 6 for an ON state.
Next, inspect 2D data for various bias point to visualise plots similar to figures 7 and 8 (OFF and ON states, respectively). We can observe that the properties of this device are dominated by valleys 1 – 3, corresponding to the three X valleys in In0.53Ga0.47As. The significantly lower effective masses of valleys 4 & 5 (L valleys), and valley 6 (Γ valley) along cross-sectional dimensions result in larger confinement-induced shifts to their associated subbands towards higher energies, rendering their impact on the properties of this device negligible.
To explore the geometrical dependence of confinement-induced energy shifts and their impact on device operation, let us simulate a similar device with a thicker channel:
- Device edit the device geometry by modifying the value of Height fields with a value of 6 nm for all three regions
- Control edit the gate voltage sweep range to [-0.2,0.85] V to cover more OFF states